The present invention relates generally to circuit testing, and more particularly to scan chains used for circuit diagnostics.
Modern circuit design incorporates methods and hardware that enable circuit testing upon completion of production, often referred to as “design for test” or “design for testability” (DFT). One DFT technique utilizes scan chains. In a scan chain system, certain latches couple together into a hardware connection known as a “scan chain.” The test system inputs a test pattern into the scan chain latches, which the system then uses to test the functionality of the circuit. As such, scan chains allow for increased testability and observability of an integrated circuit design.
Scan chains are widely used in modern IC for rapid test and debug purposes. The recent emergence of emission based test tools imposes additional requirements on scan chains. To extract useful information from emission images, a high degree of control is needed over stimuli applied to a circuit under test. In this respect, functionality of standard scan chains is quite limited.
Other limitations of standard scan chains include the scan chain adjacency problem, and broken/shorted/stuck-at wires. The scan chain adjacency problem is the inability to test certain logic state transitions when adjacent latches feed both inputs of the same 2-input AND, NAND, OR, or NOR gate. A stuck-at fault, which is typically a manufacturing defect, occurs when an input or output of a circuit is stuck at a single logic value.